ROB A. RUTENBAR
Group

PRINCIPAL INVESTIGATOR

  • Prof. Rob A. Rutenbar

ADMIN STAFF

  • Karen Stahl,  kstahl [at] Illinois [dot] edu, 217-244-7949
  • Tierra Reed (for scheduling),   tmreed [at] Illinois [dot] edu, 217-244-2758

GRAD STUDENTS

PHD ALUMNI

  • Dorothy Setliff, now at ECPI,  
    PhD Thesis: Knowledge-Based Synthesis of Custom VLSI Router Software, 1989.
  • Ramesh Harjani, now E.F Johnson Professor of ECE at U. Minnesota, 
    PhD Thesis: OASYS: A Framework for Analog Circuit Synthesis, 1989.
  • Saul Kravitz, now at MITRE,
    PhD Thesis (advised jointly with Randy Bryant): Massively Parallel Switch-Level Simula­tion: A Feasibility Study, 1989.
  • Erik Carlson, now at Armored Wolf LLC (hedge fund),
    PhD Thesis: Exploiting Massive Parallelism in VLSI Mask Verification, 1989.
  • David Garrod, now at Voci Technologies,
    PhD Thesis: Device-Level Routing of Analog Cells in ANAGRAM II, 1991.
  • John Cohn, now a Fellow at IBM,
    PhD Thesis: Device-Level Placement of Custom Analog Cells in KOAN, 1991.
  • Rajeev Jayaraman, now at Tabula,
    PhD Thesis: Massively Parallel Approaches to VLSI Layout Synthesis,  1991.
  • Balsha Robert Stanisic,
    PhD Thesis: Power Distribution Synthesis for Analog and Mixed-Signal ASICs in RAIL, 1993.
  • Emil Ochotta, now at Google,
    PhD Thesis: Automatic Synthesis of High- Performance Analog Circuits in ASTRX/OBLX, 1994.
  • Sudip Nag, now at Xilinx,
    PhD Thesis: Performance-Directed Simultaneous Place and Route for Field Programmable Gate Arrays, 1995.
  • Sujoy Mitra, now at Altera,
    PhD Thesis: Substrate-Aware Floorplanning for Mixed-Signal ASICs, 1995.
  • Gary Ellis, now at RCN Motors,
    PhD Thesis: The Physical Design of Clock Circuits, 1997.
  • Bulent Basaran, now at Synopsys,
    PhD Thesis: Techniques for Optimal Diffusion Sharing in CMOS Analog and Digital Cir­cuits, 1997.
  • Mehmet Aktuna,  now at Google,
    PhD Thesis: Layout Algorithms for Radio Frequency Circuits, 1999.
  • Rony Kay, now founder/CEO of cPacket, Inc.
    PhD Thesis: Algorithmic Approach to Design and Optimization of VLSI Intercon­nect, 1999.
  • Pascal Meier,  now at Intel
    PhD Thesis: Analysis and Design of Low-Power Multipliers, 1999.
  • Michael Krasnicki,  now at Stonesoup Labs.
    PhD Thesis: A Methodology for Distributed Simulation-Based Synthesis of Custom Analog Circuits, 2000.
  • Rodney Phelps, now at iQity Solutions,
    PhD Thesis: Analog Circuit Synthesis in an Industrial Design Flow, 2001.
  • Gi-Joon Nam (U. Michigan), now with IBM Austin Research Labs,
    PhD Thesis (joint with Karem Sakallah of UM): A Boolean Layout Approach and Its Application to FPGA Routing, 2001.
  • Prakash Krishnan (formerly “Gopalakrishnan”), now at Amazon,
    PhD Thesis: Direct Transistor Level Layout for Digital Blocks, 2003.
  • Hui Xu, now at Cadence Design Systems,
    PhD Thesis: sub-SAT: A Formulation for Relaxed Boolean Satisfiability and Its Applications, 2004.
  • Hongzhou Liu, now at Cadence Design Systems,
    PhD Thesis: Macromodeling by Data Mining in Large Analog Design Spaces, 2004.
  • Claire Fang, now at Microsoft,
    PhD Thesis: Probabilistic Interval Valued Computation: Representing and Reasoning about Uncertainty in DSP and VLSI Design, 2005.
  • Saurabh Tiwary, now at Google,  
    PhD Thesis: Scalable Trajectory Methods for On Demand Analog Macromodel Extrac­tion, 2006.
  • Zhong Xiu, now at Google,
    PhD Thesis: The Design and Implementation of a Large-Scale Placer Based on Grid-Warp­ing, 2006.
  • James D. Ma, now at Graham Capital Management (hedge fund).
    PhD Thesis: An Interval Valued Computation Methodology for Statistical Retrofitting of Existing Circuit and Technology CAD Tools, 2006.
  • Edward C. Lin,  now at Voci Technologies,.
    PhD Thesis: A High Performance Custom Hardware Backend Search Engine for a Speech Recognition System, 2007.
  • Amit Singhee, now at IBM TJ Watson Research Labs.
    PhD Thesis: Novel Algorithms for Fast Statistical Analysis of Scaled Circuits, 2008.
  • Kai Yu, now at Intel,
    PhD Thesis:  Hardware Optimization and Exploration of Feature Extraction and Feature Scoring for Speech Recognition, 2009.
  • Patrick Bourke, now at Intel in Exascale group.
    PhD Thesis: A Low-Power Hardware Architecture for Speech Recognition Search, 2011.
  • Jeffrey Johnston, now at the US National Security Agency (NSA).
    PhD Thesis: A High-Rate, Low-Power, Hardare Architecture for Speech Recognition Using Finite State Transducers, 2012.
  • Wangyang Zhang, now at Cadence Design Systems,
    PhD Thesis (with Prof Xin Li): IC Spatial Variation Modeling: Algorithms and Applications, 2012.

MASTER’S ALUMI

  • Saul Kravitz, “Multiprocessor-Based Placement by Simulated Annealing,” May 1986.
  • Erik Carlson, “A Data Structure Processor for VLSI Geometry Checking,” December 1986.
  • Rajeev Jayaraman, “Floorplanning by Annealing on a Hypercube Multiprocessor,” May 1987.
  • Emil Ochotta, “The OASYS Virtual Machine: Formalizing the OASYS Analog Synthesis Frame­work,” May 1989.
  • Dean Grannes, “A Preliminary Analysis of Decision-Making in the ELF Router-Software Genera­tor,” May 1990.
  • John Lee (advised jointly with ECE Prof. R.A. Rohrer), “Incorporating Efficient Sensitivity Analysis in AWEsim,” May 1990.
  • Sudip Nag, “Global Routing of Mixed-Signal ASICs in WREN,” April 1992.
  • Sujoy Mitra, “Detailed Routing of Mixed-Signal ASICs in WREN,” April 1992.
  • Bulent Basaran, “Latchup-Aware Placement and Parasitic-Bounded Routing of Custom Analog Cells,” April 1993.
  • K.K. Paul Lai (advised jointly with ECE Professor L.R. Carley) “Automatic Synthesis of High-Per­formance Digital Cells,” May 1994.
  • William E. Jones III (advised jointly with ECE Professor L.R. Carley), “Simultaneous Topology Selection and Sizing/Biasing for Analog Synthesis in ASTRX/OBLX,” May 1996.
  • R. Glenn Wood, “FPGA Routing and Routability Estimation by Boolean Satisfiability,” May 1996.
  • Mehmet Aktuna, “Device-Level Floorplanning for RF Circuits,” December 1996.
  • Ashish Kholi (Mechanical Engineering, advised jointly with Prof. Jon Cagan of Mechanical Engi­neering), “3D Electromechanical System Layout Via Simulated Annealing,” May 1996.
  • Michael Krasnicki, “Generalized Analog Circuit Synthesis,” December 1997.
  • Christopher Dunn, “Improved Analog Transistor Layout in KOAN,” Dec. 1997.
  • Brian Bernberg, “Layout and Technology Mapping Optimizations to Support Multiple-Rail Low- Power Circuits,” May 1998.
  • Prakash Gopalakrishnan, “Transistor-Level Placement,” May 1999.
  • Fang Fang, “Lightweight Arithmetic IP – Customizable Computational Cores for Mobile Multimedia Appliances,” December 2001.
  • Suzanne Fowler, “Placement by Grid Warping,” December 2001.
  • Amit Singhee, “Nearest Neighbor Queries for Analog CAD Applications,” May 2002.
  • Saurabh Tiwary, “Composable Macromodels–A Strategy for Automated Fitting of non-linear analog circuits,” Dec. 2002.
  • Zhong Xiu, “VLSI Component Placement by Grid Warping,” May 2003.
  • Dong Chen, “Pipelined A/D Converter Synthesis,” May 2003.
  • Edward Lin, “A First-Generation Hardware Reference Model for a Speech Recognition Engine,” May 2003.
  • Smriti Gupta, “Formal Verification of Analog Designs,” May 2004.
  • Patrick Bourke, “A Queue-Based Architecture for Hardware Speech Recognition,” May 2004.
  • Sonia Singhal, “Large-Scale Placement by Triangular-Mesh Warping,” Dec. 2007.
  • Pragati Tiwary, “Application of Stochastic Pijavskij Tunneling (SPT) Optimizer for Synthesis of System Level Mixed-Signal,” August, 2008.
  • Qingxing Zhang, 2009.
  • Jeffrey Johnston, 2009.

 

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