- “Taking Computing+Data Wide Across the Curriculum: The Illinois CS+X and MCS-DS Degree Programs”, invited talk at EECS Dept, University of California Berkeley, Berkeley CA, February 2017.
- “Hardware Inference Accelerators for Machine Learning,” Invited Edward McCluskey Memorial Keynot, IEEE International Test Conference (ITC), Fort Worth, TX, November 2016. Video is here.
- “What’s Up With Analog CAD…?” Invited keynote, TxACE Texas Analog Center of Excellence 2016 Annual Symposium, Dallas TX, October 2016.
- “Teaching EDA at Planetary Scale: Reflections on the First EDA MOOCs,” IEEE Council on Electronic Design Automation (CEDA) Distinguished Lecture at ACM/IEEE Int’l Conference on CAD (ICCAD), Santa Clara, CA, November, 2014.
- “Integrated Circuits at the (Energy Constrained) End of Silicon Scaling, “ invited talk at workshop: ECO2 Computing: Towards Ecologically-Friendly & Economical IT. Organized by Prof Babak Falsafi, EPFL, Lausanne Switzerland, June 2010.
- “Using the Mathematics of Money to Understand the Statistics of Nanoscale Circuits,” invited talk on “New Frontiers” at 2010 Semiconductor Research Corporation TECHCON Conference, Austin TX, October 2010.
BOOKS & BOOK CHAPTERS
- Patrick Bourke, Kai Yu and Rob A. Rutenbar, “Mobile Speech Hardware: The Case for Custom Silicon,” Chapter 2 in Speech in Mobile and Pervasive Environments, Nitendra Rajput and Amit Anil Nanavati, Eds., Wiley, pp. 7-56, 2012. ISBN: 0470694351.
- Extreme Statistics in Nanoscale Memory Design, Amith Singhee and Rob A. Rutenbar (Eds.), pp. 203-240, Springer, 2010. ISBN: 1441966056.
- My Amazon Author page, for all my books, is here.
MACHINE LEARNING AND INFERENCE IN SILICON
- Jungwook Choi and Rob A. Rutenbar, “Video-Rate Stereo Matching Using Markov Random Field TRW-S Inference on a Hybrid CPU+FPGA Computing Platform,” in Proc. ACM Int’l Symposium on FPGAs (ISFPGA), February 2013.
- Eric P. Kim, Jungwook Choi, Naresh R. Shanbhag, and Rob A. Rutenbar, “Error Resilient and Energy Efficient MRF Message Passing Based Stereo Matching,” IEEE Transactions on VLSI Systems (TVLSI), Vol. 24, No. 3, March 2016.
- Glenn Ko and Rob A. Rutenbar, “A Case Study of Machine Learning Hardware: Real-Time Source Separation using Markov Random Fields via Sampling-based Inference”, IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), April 2017.
SPEECH RECOGNITION IN SILICON
- E.C. Lin and R.A. Rutenbar, “A Multi-FPGA 10x-Real-Time High-Speed Search Engine for a 5000-Word Vocabulary Speech Recognizer ,” Proc. 2009 ACM International Symposium on FPGAs (ISFPGA), February 2009.
- Kai Yu and Rob A. Rutenbar, “Profiling Large-Vocabulary Continuous Speech Recognition on Embedded Devices: A Hardware Resource Sensitivity Analysis,” Proc Interspeech 2009.
- Jeffrey R. Johnston and Rob A. Rutenbar, “A High Rate Low Power, ASIC Speech Decoder Using Finite State Transducers,” Proc. ASAP 2012.
STATISTICS FOR NANOSCALE SILICON
- A. Singhee, R. A. Rutenbar, “Statistical Blockade: Very Fast Statistical Simulation and Modeling of Rare Circuit Events, and its Application to Memory Design,” IEEE Trans. CAD, vol. 28, No. 8, August 2009.
- Amith Singhee and Rob A. Rutenbar, “Why Quasi-Monte Carlo is Better Than Monte Carlo or Latin Hypercube Sampling for Statistical Circuit Analysis,” IEEE Transactions on CAD, Vol. 29, No. 11, pp. 1763-1776, November 2010.
- Wangyang Zhang, Xin Li, Frank Liu, Emrah Acar, Rob A. Rutenbar, R. Shawn Blanton, “Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits,” IEEE Trans. On CAD, Vol. 30, No. 12, pp. 1814 – 1827, December 2011.
- Michael Krasnicki, Rodney Phelps, Rob A. Rutenbar, L. Richard Carley “MAELSTROM: Efficient Simulation-Based Synthesis for Custom Analog Cells,” in Proc. ACM/IEEE Design Automation Conference, June 1999.
- Rodney Phelps, Michael Krasnicki, Rob A. Rutenbar, L. Richard Carley, “A Case Study of Synthesis for Industrial-Scale Analog IP: Redesign of the Equalizer/Filter Frontend for an ADSL CODEC,” Proc. ACM/IEEE Design Automation Conference, June 2000.
- R. Harjani, R. A. Rutenbar and L. R. Carley, “OASYS: A Framework for Analog Circuit Synthesis,” IEEE Trans. On CAD. Vol. 8, no, 2, December 1989.
- Xiu, James D. Ma, Suzanne M. Fowler, Rob A. Rutenbar, “Large-Scale Placement by Grid Warping” Proc. of ACM/IEEE Design Automation Conference, June 2004.
- Rony Kay and Rob A. Rutenbar, “Wire Packing: A Strong Formulation of Crosstalk-Aware Chip- Level Track/Layer Assignment with an Efficient Integer Programming Solution,” IEEE Trans. CAD, vol. 20, no. 5, May 2001, pp 672 -679.
- Gi-Joon Nam, Fadi Aloul, Karem Sakallah, Rob A. Rutenbar, “A Comparative Study of Two Boolean Formulations of FPGA Detailed Routing,” IEEE Transaction on Computers, vol 53, no 6, June 2004.
FORMAL VERIFICATION & SIMULATION
- Smriti Gupta, Bruce Krogh, Rob A. Rutenbar, “Towards Formal Verification of Analog Designs,” Proc. ACM/IEEE Int’l Conference on CAD, Nov. 2004.
- G. Frehse, B. H. Krogh, and R. A. Rutenbar, “Verifying Analog Oscillator Circuits using Forward/ Backward Refinement,” Proceedings of the 9th Conference on Design, Automation and Test in Europe (DATE 06), March 2006.
- Saurabh Tiwary, Rob A. Rutenbar, “Scalable Trajectory Methods for On-Demand Analog Macro-model Extraction,” Proc. ACM/IEEE Design Automation Conference, June 2005.
- Georges Gielen and Rob A. Rutenbar, “Computer Aided Design of Analog & Mixed Signal Inte-grated Circuits,” Proceedings of the IEEE, vol. 88, no.12, December 2000.
- Jaijeet Roychowdhury, Rob A. Rutenbar and Georges Gielen, “Hierarchical Modeling, Optimization and Synthesis for System-Level Analog and RF Designs,” Proceedings of the IEEE, vol. 95, no. 3, March 2007.
- Benton H. Calhoun, Yu Cao, Xin Li, Ken Mai, Lawrence T. Pileggi, Rob A. Rutenbar and Kenneth L. Shepard, “Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS,” Proceedings of the IEEE, Vol. 96, No. 2, pages 343-365, February 2008.