Bridging the Synthesis Gap from Circuits to Systems for Scaled Mixed-Signal Silicon


Group Researchers: Pragati Tiwary, Saurabh Tiwary, Dong Chen, Senthil Velu

Collaborators: Tamal Mukherjee, CMU; Jeyanandh Paramesh, CMU; Yu-tsun Chien, ITRI, Taiwan

Synthesis tools for cell-level analog building blocks (10-100 devices) have recently made the transition from academic prototypes to commercial products. These tools can help to size, bias, center, optimize and lay out critical analog and RF circuits. Unfortunately, they do not scale directly to system level, where we may have 10-100 blocks, integrated with many digital functions, using problematic scaled devices better suited for NAND gates than opamps. A key obstacle is the essential architecture of the today’s cell-level tools: they employ simulation-based synthesis, and rely on full SPICE level evaluation of each evolving solution candidate, in a large global-optimization framework, distributed across networked workstations. The strategy has been the key enabler for cell-level designs that are ‘trustworthy’ to designers. However, we cannot simulate system-level designs rapidly enough to use this paradigm. Alternatives have been proposed, none successfully. This projects is developing novel synthesis strategies based on three key ideas: (1) we strive to reuse (i.e., to respect) the existing models used by practicing system designers; (2) we optimally leverage existing cell-level optimization tools; (3) we bring first-order statistical optimization into the same framework, by extracting statistical tradeoff models from key circuits, and inserting these into the system-level design problem.

Key Papers/Talks

  • S.K. Tiwary, S. Velu, R.A. Rutenbar, T. Mukherjee, “Pareto-Optimal Modeling for Efficient PLL Optimization,” Technical Proceedings of the 2004 NSTI Nanotechnology Conference and Trade Show, 2004. pdf
  • Yu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma, Rob A. Rutenbar, and Tamal Mukherjee,”Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters,” in Design Automation and Test in Europe (DATE 2005), March 2005, pp. 279-280. pdf
  • R.A. Rutenbar, “Design Automation for Analog: The Next Generation of Tool Challenges,” 1st IBM Academy Conference on Analog Design, Technology, Modeling and Tools, IBM T.J. Watson Research Labs, Sept. 2006. pdf
  • R.A. Rutenbar, “Design Automation for Analog: The Next Generation of Tool Challenges,” IEEE/ACM International Conference on Computer-Aided Design, 2006. ICCAD ’06. Nov. 2006. pdf
  • R.A. Rutenbar, G.G.E. Gielen, J. Roychowdhury, “Hierarchical Modeling, Optimization, and Synthesis for System-Level Analog and RF Designs,” Proceedings of the IEEE, Vol. 95, No. 3, March 1997. pdf
  • S. Tiwary, P. Tiwary, R.A. Rutenbar, “Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration,” Proc ACM/IEEE Design Automation Conf, June 2006. pdf

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